General Description
The RT5713 is a high efficiency synchronous step-down converter featuring typ. 360nA quiescent current. This document explains the function and use of the RT5713 evaluation board (EVB), and provides information to related setting of the evaluation board.
Performance Specification Summary
Summary of the RT5713 Evaluation Board performance specificiaiton is provided in Table 1. The ambient temperature is 25°C.
Table 1. RT5713 Evaluation Board Performance Specification Summary
Specification
|
Test Conditions
|
Min
|
Typ
|
Max
|
Unit
|
Input Voltage Range
|
|
2.2
|
--
|
5.5
|
V
|
Output Current
|
|
0
|
--
|
0.4
|
A
|
Operation Frequency
|
|
--
|
1.2
|
--
|
MHz
|
IQ_Non-SW
|
VOUT = 1.8V, IOUT = 0A, EN = VIN, non-switching
|
--
|
360
|
800
|
nA
|
IQSW
|
VOUT = 1.8V, IOUT = 0A, EN = VIN, switching
|
--
|
460
|
1200
|
ISHDN
|
EN = GND
|
--
|
0.2
|
1
|
µA
|
VOUT_ACC10
|
VOUT = 1.8V, IOUT = 10mA
|
-2.5
|
--
|
2.5
|
%
|
VOUT_ACC100
|
VOUT = 1.8V, IOUT = 100mA
|
-2
|
--
|
2
|
%
|
Power-up Procedure
Suggestion Required Equipments
- RT5713 Evaluation Board
- DC power supply capable of at least 5.5V and 3A
- Electronic load capable of 3A
- Function Generator
- Oscilloscope
Quick Start Procedures
The Evaluation Board is fully assembled and tested. Follow the steps below to verify board operation. Do not turn on supplies until all connections are made. When measuring the output voltage ripple, care must be taken to avoid a long ground lead on the oscilloscope probe. Measure the output voltage ripple by touching the probe tip and ground ring directly across the last output capacitor.
Proper measurement equipment setup and follow the procedure below.
1) Set output voltage by VSEL pin (L for Output-1, H for Output-2).
2) With power off, connect the input power supply to VIN and GND pins.
3) With power off, connect the electronic load between the VOUT and nearest GND pins.
4) Turn on the power supply at the input. Make sure that the input voltage does not exceeds 5.5V on the Evaluation Board.
5) Enabled the RT5713 by EN pin. When the EN pin is higher than the threshold of logic-high IC goes to normal operation; When EN pin High transfer Low into shutdown mode, the converter stops switching, internal control circuitry is turned off and trigger discharge function. That discharge function will close after count 10ms (typ.).
6) To verify the output voltage VOUT. If VSEL connect to L, output voltage of the RT5713 measurement is Output-1; If VSEL connect to H, output voltage of the RT5713 measurement is Output-2.
7) Check for the proper output voltage using a voltmeter.
8) Once the proper output voltage is established, adjust the load within the operating ranges and observe the output voltage regulation, ripple voltage, efficiency and other performance.
Detailed Description of Hardware
Headers Description and Placement
Carefully inspect all the components used in the EVB according to the following Bill of Materials table, and then make sure all the components are undamaged and correctly installed. If there is any missing or damaged component, which may occur during transportation, please contact our distributors or e-mail us at evb_service@richtek.com.
Test Points
The EVB is provided with the test points and pin names listed in the table below.
Test Point/
Pin Name
|
Function
|
VIN
|
Input voltage.
|
VOUT
|
Output voltage.
|
GND
|
Ground.
|
EN
|
Enable test point.
|
LX
|
Switching signal
|
VSEL
|
Output voltage select.
|
Output Voltage Selection
The RT5713 provides 2 level output voltages which can be programmed via the voltage select pin VSEL.
Table 2 indicates the setting to indivdual output voltage.
Table 2. Output Voltage Setting
Output-1 (VSEL = 0)
|
Code
|
Output-2 (VSEL = 1)
|
Code
|
0.525V
|
A
|
0.525V
|
A
|
0.55V
|
B
|
0.55V
|
B
|
0.58V
|
C
|
0.58V
|
C
|
0.6V
|
D
|
0.6V
|
D
|
0.625V
|
E
|
0.625V
|
E
|
0.65V
|
F
|
0.65V
|
F
|
0.675V
|
G
|
0.675V
|
G
|
0.7V
|
H
|
0.7V
|
H
|
0.75V
|
J
|
0.75V
|
J
|
0.8V
|
K
|
0.8V
|
K
|
0.85V
|
L
|
0.85V
|
L
|
0.9V
|
M
|
0.9V
|
M
|
0.95V
|
N
|
0.95V
|
N
|
1V
|
P
|
1V
|
P
|
1.05V
|
Q
|
1.05V
|
Q
|
1.1V
|
R
|
1.1V
|
R
|
1.15V
|
S
|
1.15V
|
S
|
1.2V
|
T
|
1.2V
|
T
|
1.3V
|
U
|
1.3V
|
U
|
1.4V
|
V
|
1.4V
|
V
|
1.5V
|
W
|
1.5V
|
W
|
1.6V
|
Y
|
1.6V
|
Y
|
1.7V
|
Z
|
1.7V
|
Z
|
1.8V
|
1
|
1.8V
|
1
|
1.9V
|
2
|
1.9V
|
2
|
2V
|
3
|
2V
|
3
|
2.1V
|
4
|
2.1V
|
4
|
2.5V
|
5
|
2.5V
|
5
|
2.75V
|
6
|
2.75V
|
6
|
3V
|
7
|
3V
|
7
|
3.3V
|
8
|
3.3V
|
8
|
4V
|
9
|
4V
|
9
|
Bill of Materials
|
RT5713 WL-CSP Package
|
|
Reference
|
Count
|
Part Number
|
Value
|
Description
|
Package
|
Manufacturer
|
U1
|
1
|
RT5713-K1WSC
|
RT5713-K1WSC
|
Step-Down Converter
|
WL-CSP-6B 1.415x0.885 (BSC)
|
RICHTEK
|
C3
|
1
|
GRM155R60J475ME47
|
4.7µF
|
4.7µF/6.3V/X5R
|
0402
|
Murata
|
C4
|
1
|
GRM155R60J106ME15
|
10µF
|
10µF/6.3V/X5R
|
0402
|
Murata
|
L1
|
1
|
DFE201610E-2R2M=P2
|
2.2µH
|
2.2µH
|
2016
|
TDK
|
|
|
|
|
|
|
|
|
|
Typical Applications
EVB Schematic Diagram
For RT5713 WL-CSP Package
1. The capacitance values of the input and output capacitors will influence the input and output voltage ripple.
2. MLCC capacitors have degrading capacitance at DC bias voltage, and especially smaller size MLCC capacitors will have much lower capacitance.
Measure Result
Efficiency vs. Output Current
|
Load Regulation vs. Output Current
|
|
|
Output Voltage Ripple vs. Output Current
|
Quiescent Current vs. Input Voltage
|
|
|
Shut Down Current vs. Input Voltage
|
Output Voltage Error vs. Temperature
|
|
|
PSM Mode Operation
|
PWM Mode Operation
|
|
|
Power On with Light Load
|
Power On with Heavy Load
|
|
|
Load Transient Response
|
Load Transient Response
|
|
|
Note: When measuring the input or output voltage ripple, care must be taken to avoid a long ground lead on the oscilloscope probe. Measure the output voltage ripple by touching the probe tip directly across the output capacitor.
Evaluation Board Layout
Figure 1 to Figure 4 are RT5713 WL-CSP package Evaluation Board layout. This board size is 70mm x 50mm and is constructed on four-layer PCB.
Figure 1. Top View (1st layer)
Figure 2. PCB Layout—Inner Side (2nd Layer)
Figure 3. PCB Layout—Inner Side (3rd Layer)
Figure 4. Bottom View (4th Layer)